The present invention generally relates to methods for checking and keeping track of parity errors with regard to memory address locations.
Parity checking is an error detection technique that tests the integrity of digital data in memory. Parity checking adds an extra parity cell to each byte of memory and an extra parity bit to each byte transmitted. The value of the ninth bit (0 or 1) depends on the pattern of the byte's eight bits. Each time a byte is transferred or transmitted, the parity bit is tested by memory controller circuits on the motherboard.
“Even” parity systems make the parity bit 1 when an even number of 1 bits are in the byte, while “odd” parity systems make the parity bit 1 when an an odd number of 1 bits are present. Parity checking cannot detect the condition in which two data bits are in error, because they cancel themselves—I . . . , the parity bit would still be correct for that sequence of 0s and 1s.
The present invention is directed at an improved method and device for checking and keeping track of parity errors with regard to memory address locations.